4.7 A 2.7 Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI Systems

fulfills the demands of future high speed, fault tolerant and smart interconnect systems is presented. By using code- division multiple access (CDMA) techniques in the transmitter and receiver chips, a CDMA-Interconnect (CDMA-I) system has been demonstrated that enables reconfigurability while achieving an aggregate throughput of 2.7Gb/s. The achieved throughput is several orders of magnitude higher than prior work [2]. The proposed CDMA-I uses pseudo-noise (PN) codes to separate different users and I/O ports on a shared bus. It modulates the data into a spread spectrum signal by orthogonal Walsh codes or PN codes such as Gold and Kasami codes. The code-modulated signal from each I/O port is combined into a multi-level signal for transmission. For N I/O ports, the minimum spread ratio is log2 N+1. Reconfigurability is a unique advantage of CDMA-I as th