High-performance interconnects: An integration overview

The Information Revolution and enabling era of silicon ul-tralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional tran-sistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipa-tion concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement. Keywords—Aluminum metallization, ball grid array (BGA), bandwidth, bottom antireflection coating (BARC), chemical–me-chanical planarization (CMP), code-division multiple access, coplanar waveguides, copper metallization, crosstalk, diffusion barrier, dual damascene, electrochemical deposition (ECD), elec-tromigration, frequency-division multiple access (FDMA), global interconnects, IC packaging, interconnect, interlayer dielectric (ILD), International Technology Roadmap for Semiconductors (ITRS), intrametal dielectric (IMD), latency, local interconnects, low-k dielectrics, microstrip transmission line (MTL), Moore’s law, optical interconnects, physical vapor deposition, RC delay, RC parasitics, RF interconnects, 3-D interconnects