Embedded program timing analysis based on path clustering and architecture classificaton

Formal Program running time verication is an impor-tant issue in system design required for performance op-timization under " rst-time-right " design constraints and for real-time system verication. Simulation based ap-proaches or simple instruction counting are not appropri-ate and risky for more complex architectures in particu-lar with data dependent execution paths. Formal analysis techniques have suered from loose timing bounds leading to signicant performance penalties when strictly adhered to. We present an approach which combines simulation and formal techniques in a safe way to improve analysis precision and tighten the timing bounds. Using a set of processor parameters, it is adaptable to arbitrary processor architectures. The results show an unprecedented analy-sis precision allowing to reduce performance overhead for provably correct system or interface timing.