RELAXED SIGE ON INSULATOR FABRICATED VIA WAFER BONDING AND LAYER TRANSFER: ETCH-BACK AND SMART-CUT ALTERNATIVES

SiGe on Insulator (SiGeOI) is an improved substrate for MOS devices since it combines both the benefits of an insulating substrate with those of a SiGe device layer. The fabrication process begins with the UHV-CVD growth of a SiGe graded layer on a Si substrate, followed by CMP to smooth the surface. For the etch-back process, a regrowth step is performed during which a strained Si layer etch-stop is grown followed by Si0.75Ge0.25. The substrate is bonded to an oxidized Si handle wafer, and the Si backside of the SiGe wafer is ground. Various etches are then used to remove the remaining SiGe, while stopping on the strained Si. On the other hand, for the Smart-cut approach, the CMPed SiGe wafer is transferred onto an oxidized Si handle wafer. In particular, the SiGe wafer is implanted with hydrogen to form a buried hydrogen-rich layer, then bonded and annealed to accomplish splitting at the hydrogen-rich region