A reconfigurable architecture for hybrid CMOS/nanodevice circuits

This report describes a preliminary evaluation of perfor-mance of a cell-FPGA-like architecture for future hybrid “CMOL ” circuits. Such circuits will combine a semiconduc-tor-transistor (CMOS) stack and a two-level nanowire cross-bar with molecular-scale two-terminal nanodevices (program-mable diodes) formed at each crosspoint. Our cell-based architecture is based on a uniform CMOL fabric of “tiles”. Each tile consists of 12 four-transistor basic cells and one (four times larger) latch cell. Due to high density of nan-odevices, which may be used for both logic and routing func-tions, CMOL FPGA may be reconfigured around defective nanodevices to provide high defect tolerance. Using a semi-custom set of design automation tools we have evaluated CMOL FPGA performance for the Toronto 20 benchmark set, so far without optimization of several parameters in-cluding the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide a density advantage of more than two orders of magnitude over the traditional CMOS FPGA with the same CMOS design rules, at comparable time delay, acceptable power consumption and potentially high defect tolerance