Low Power Design of Johnson Counter Using DDFF Featuring Efficient Embedded Logic and Clock Gating

Abstract—In this paper, we have proposed a power efficient design of a 4-bit up-down Johnson counter by using Dual Dynamic Node Pulsed Flip-flop(DDFF) featuring efficient embedded logic module(DDFF-ELM) and then clock gating is incorporated in order to reduce the power dissipation further. The proposed design employs a DDFF which mainly reduces the power consumption by eliminating the large capacitance present in the pre-charge node of several existing flip-flop designs by separately driving the output pull-up and pull-down transistors by following a split dynamic node structure. This reduces the power up to 40 % compared to conventional architectures of the flip-flops. Then the Embedded logic module is an efficient method to incorporate complex logic functions into the flip-flop. Clock gating is applied to reduce the power consumption up to 50 % due to unnecessary clock activities. Key words—Johnson counter, DDFF, DDFF-ELM, clock gating, XCFF, CDMFF, low power. I