Through Silicon Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs

Individual dies in 3D integrated circuits are connected using through-silicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied thoroughly in the literature. In this paper, we analyze the impact of TSVs on silicon area and wirelength. We derive a new 3D wirelength distri-bution model considering TSV size. Based on this new prediction model, we explain the impact of several design parameters newly introduced in 3D ICs. We also present a case study to show how the model can help make early design decisions for 3D ICs