Swizzle-Switch Networks for Many-Core Systems

Abstract—This work revisits the design of crossbar and high-radix interconnects in light of advances in circuit and layout techniques that improve crossbar scalability, obviating the need for deep multi-stage networks. We employ a new building block, the Swizzle-Switch—an energy- and area-efficient switching ele-ment that can readily scale to radix 64—that has recently been validated via silicon test chips in 45 nm technology.We evaluate the Swizzle-Switch as both the high-radix building block of a Flattened Butterfly and as a single-stage interconnect, the Swizzle-Switch Network. In the process we address the architectural and layout challenges associated with centralized crossbar systems. Com-pared to a conventional Mesh, the Flattened Butterfly provides a 15 % performance improvement with a 2.5 reduction in the standard deviation of on-chip access times. The Swizzle-Switch Network achieves further gains, providing a 21 % improvement in performance, a 3 reduction in on-chip access variability, a 33% reduction in interconnect power, and a 25 % reduction in total system energy while only increasing chip area by 7%. Finally, this paper details a 3-D integrated version of the Swizzle-Switch Network, showing up to a 30 % gain in performance over the 2-D Swizzle-Switch Network for benchmarks sensitive to interconnect latency. One major concern with 3-D designs is thermal dissipa-tion. We show through detailed thermal analysis that with the highly energy-efficient Swizzle-Switch Network design that the thermal budget is well within that of passive cooling solutions. Index Terms—Crossbars, manycore systems, multicore pro-cessing, network-on-chip, network topology, on-chip intercon-nects, parallel architectures. I