Power aware microarchitecture resource scaling

In this paper we present a strategy for run-time profiling to op-timize the configuration of a microprocessor dynamically so as to save power with minimum performance penalty. The configuration of the processor changes according to the parallelism in the run-ning program. Experiments on some benchmark programs show good savings in total energy consumption; we have observed a de-crease of up to 23 % in energy/cycle and up to 8 % in energy per instruction. Our proposed approach can be used for energy-aware computing in either portable applications or in desktop environ-ments where power density is becoming a concern. This approach can also be incorporated in larger power management strategies like ACPI. 1