Efficiency Trends and Limits from Comprehensive Microarchitectural Adaptivity

Increasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and com-putational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interac-tions between recent advances in (a) sampling, (b) predictive mod-eling, and (c) optimization heuristics. This framework enables qual-itatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and compre-hensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B points. With frequent sub-application reconfiguration and a fully recon-figurable hardware substrate, adaptive microarchitectures achieve bips3/w efficiency gains of up to 5.3x (median 2.4x) relative to their static counterparts already optimized for a given application. This 5.3x efficiency gain is derived from a 1.6x performance gain and 0.8x power reduction. Although several applications achieve a significant fraction of their potential efficiency with as few as three adaptive parameters, the three most significant parameters differ across applications. These differences motivate a hardware substrate capable of comprehensive adaptivity to meet these diverse application requirements