A comparison of FPGA platforms through SAR/ATR algorithm implementation

As computing platforms gain greater and greater computational power, new applications that previously were unthinkable are being developed. One such application is the ability to automatically identify objects in radar images called Automatic Tar-get Recognition (ATR). This thesis specically deals with ATR algorithms developed to search for objects in Synthetic Aperture Radar (SAR) images. The algorithms require more computational power than is currently available in any platforms. These algorithms were used as a tool to compare two recongurable hardware platforms because of these high computational requirements. Two implementations of ATR for SAR have been de-veloped to compare Teramac and Splash-2 Field Programmable Gate Array (FPGA) based platforms. This comparison shows Teramac's strength as an exploratory platform and Splash-2's strength as an implementation platform for linear systolic array designs