Design of Cache Memory Cell for Leakage Power Reduction

Abstract — This paper represents a successful comparison of 5T cell with 6T cell. Leakage power of conventional 6T cell at 0.18 µm technology has been calculated and is found to be 37.32 pW. Same technology has been implemented on the 5T cell, by which leakage power has been reduced by 37.59%.Various leakage reduction techniques such as Autobackgate Controlled Multi-threshold CMOS (ABC-MTCMOS), Gated VDD and Dynamic Voltage Scaling (DVS) has been discussed and applied on conventional 6T cache memory cell and same has been apply on 5T cell and compared. Mentor graphics software is for the simulation of the above mentioned SRAM cel