BPSK, QPSK MODULATOR SIMULATION MODEL

This project arised out of the diploma thesis called „BPSK, QPSK Modulator and Demo-dulator“. Design facilities of the modulator in the FPGA are presented in this paper using a VHDL language and DDS component in the Xilinx ISE development tool. The basic buil-ding block is a DDS synthesizer accessible as an intelectual property core. The result is a modulator simulation model with possibility of implementation in FPGA. 1