Add to ORKGA new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presented. The architecture is based on a fine-grain software-programmable SIMD array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analogue microprocessor concept. In a 0.6µm CMOS process the cell size is equal to 98.6µm×98.6µm. A prototype 21×21 array chip executes over 1.1 GIPS (Giga Instructions Per Second) while dissipating below 40mW of power and demonstrates a real-time performance on a variety of early vision tasks. 1
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO ...
Abstract—This paper describes an architecture and implemen-tation of a digital vision chip that feat...
A high-speed analog VLSI image acquisition and low-level image processing system are presented. The ...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
Abstract − This paper describes an analogue processing element (APE) suitable for high-density image...
Abstract A high speed analog VLSI image acquisition and low-level image processing system is present...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
Abstract — In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pi...
This paper presents the latest implementation of the SIMD Current-mode Analogue Matrix Processor arc...
A programmable vision chip for real-time vision applications is presented. The chip architecture is ...
Vision chips are microelectronic devices which combine image sensing and processing on a single sili...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO ...
Abstract—This paper describes an architecture and implemen-tation of a digital vision chip that feat...
A high-speed analog VLSI image acquisition and low-level image processing system are presented. The ...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
Abstract − This paper describes an analogue processing element (APE) suitable for high-density image...
Abstract A high speed analog VLSI image acquisition and low-level image processing system is present...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
International audienceA high speed analog VLSI image acquisition and low-level image processing syst...
Abstract — In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pi...
This paper presents the latest implementation of the SIMD Current-mode Analogue Matrix Processor arc...
A programmable vision chip for real-time vision applications is presented. The chip architecture is ...
Vision chips are microelectronic devices which combine image sensing and processing on a single sili...
This paper reports a 176×144-pixel smart image sensor designed and fabricated in a 0.35µm CMOS-OPTO ...
Abstract—This paper describes an architecture and implemen-tation of a digital vision chip that feat...
A high-speed analog VLSI image acquisition and low-level image processing system are presented. The ...