Multi-functional interconnect cooptimization for fast and reliable 3D stacked ICs

Heat removal and power delivery have become two major relia-bility concerns in 3D stacked IC technology. For thermal prob-lem, two possible solutions exist: thermal-through-silicon-vias (T-TSVs) and micro-fluidic channel (MFC) based liquid cooling. In case of power delivery, a highly complex power distribution net-work is required to deliver currents reliably to all parts of the 3D stacked IC while suppressing the power supply noise to an ac-ceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. This is be-cause the signal, power, and thermal interconnects are all compet-ing for routing space. In this paper, we present a co-optimization methodology for the signal, power, and thermal interconnects for 3D stacked ICs based on design of experiments (DOE) and re-sponse surface method (RSM). The goal is to improve performance