Noise margin and leakage in ultra-low leakage SRAM cell design

Abstract—Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may be made very small for improved performance. Also, the ramifications of threshold uncertainty due to random dopant fluctuations are investigated, and it is shown that chip performance will be adversely affected by this phenomenon. Index Terms—CMOSFETS, CMOS memory integrated circuits, random access memory (RAM). I