MePoEfAr: Memory and Power Efficient Architecture for Embedded Microcontrollers

Microcontroller based embedded systems have witnessed enormous growth in recent decades. Microcontrollers are the most versatile products found in most of the market segments and in several product families spanning from 4-bit to 64-bit processors. The application domain is such that for some ap-plications only a little functionality is required; for instance, when used as a controller for a simple user interface. In other applications, the function-ality demands are high, such as the demand for floating-point calculations and signal processing. Microcontrollers have to meet these demands, while being smaller in size and power efficient. Since memory occupies a large share of area in a microcontroller and contributes the most towards power consumption, the architecture has to be memory efficient. Particularly, for applications using a matrix of processors (as in multi-core architectures), each with its own program memory, the program memory and power effi-ciencies are a major design goal. The memory efficiency of the instruction set, which also implies power efficiency, is an important factor which need