Design and Evaluation of a Coarse-Grained Reconfigurable Architecture

Abstract – Coarse-grained reconfigurable architectures have become more attractive with the increasing requirement of more flexibility and higher performance in embedded systems design. In this paper, we suggest a design space exploration flow that enables effective optimization of reconfigurable architectures through SystemC Modeling. In the suggested flow, applica-tion-to-architecture mapping process tries loop pipelining technique to find a better performance. According to the result of design space exploration, we implement a coarse-grained re-configurable architecture in RT level. For the evaluation, we take H.263 encoder as the application. Estimated results show significant improvement over previous approaches