Low-power adaptive pipelined MPSoCs for multimedia: an h.264 video encoder case study

Pipelined MPSoCs provide a high throughput implementation platform for multimedia applications, with reduced design time and improved flexibility. Typically a pipelined MPSoC is balanced at design-time us-ing worst-case parameters. Where there is a widely varying workload, such designs consume exorbitant amount of power. In this paper, we propose a novel adaptive pipelined MPSoC architecture that adapts it-self to varying workloads. Our architecture consists of Main Proces-sors and Auxiliary Processors with a distributed run-time balancing ap-proach, where each Main Processor, independent of other Main Proces-sors, decides for itself the number of required Auxiliary Processors at run-time depending on its varying workload. The proposed run-time bal-ancing approach is based on off-line statistical information along with workload prediction and run-time monitoring of current and previous workloads ’ execution times. We exploited the adaptability of our ar-chitecture through a case study on an H.264 video encoder supporting HD720p at 30 fps, where clock- and power-gating were used to deacti-vate idle Auxiliary Processors during low workload periods. The results show that an adaptive pipelined MPSoC provides energy savings of up to 34 % and 40 % for clock- and power-gating based deactivation of Auxil-iary Processors respectively with a minimum throughput of 29 fps when compared to a design-time balanced pipelined MPSoC