A Gaussian Noise Generator for Hardware-Based Simulations

Abstract—Hardware simulation offers the potential of improving code evaluation speed by orders of magnitude over workstation or PC-based simulation. We describe a hardware-based Gaussian noise generator used as a key component in a hardware simulation system, for exploring channel code behavior at very low bit error rates (BERs) in the range of 109 to 1010. The main novelty is the design and use of nonuniform piecewise linear approximations in computing trigonometric and logarithmic functions. The parameters of the approximation are chosen carefully to enable rapid computation of coefficients from the inputs while still retaining high fidelity to the modeled functions. The output of the noise generator accurately models a true Gaussian Probability Density Function (PDF) even at very high values. Its properties are explored using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test, and 2) an application for decoding of Low-Density Parity-Check (LDPC) codes. An implementation at 133MHz on a Xilinx Virtex-II XC2V4000-6 FPGA produces 133 million samples per second, which is seven times faster than a 2.6GHz Pentium-IV PC; another implementation on a Xilinx Spartan-IIE XC2S300E-7 FPGA at 62MHz is capable of a three times speedup. The performance can be improved by exploiting parallelism: An XC2V4000-6 FPGA with nine parallel instances of the noise generator at 105MHz can run 50 times faster than a 2.6GHz Pentium-IV PC. We illustrate the deterioration of clock speed with the increase in the number of instances. Index Terms—Algorithms implemented in hardware, error-checking, gate arrays, simulation.