A Novel Scheme for Low-Power SRAM using Active-DRG BL Charge Recycling for Read/Write Operations and Leakage Reduction for Embedded/Multimedia Memory Applications

ABSTRACT – The Low-Power and High-Performance CMOS devices is an industry buzzword these days. Among the various embedded memory technologies, SRAM is able to provide the highest performance while maintaining low standby power consumption. High leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Therefore, identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for battery operated portable low-power applications. This paper targets the power reduction in a conventional SRAM at the circuit level by reducing the leakage power consumption. To the best of my knowledge, this paper proposes a novel approach for over-all power reduction in an SRAM by introducing the Active-DRG configuration with the Bit-Line CR technique (W/R) for the first time. It is proposed that while the memory is in the active mode, the power optimization is achieved through BL-CR and when the memory is not in use, i.e., in the standby mode, the leakage power is achieved through DRG scheme. The technique is given the name as, Active-DRG Scheme. In this new memory architecture the power reduction is achieved for both the dynamic and the standby mode