Optimizing Remote Accesses for Offloaded Kernels: Application to HighLevel Synthesis for FPGA

Some data- and compute-intensive applications can be ac-celerated by offloading portions of codes to platforms such as GPGPUs or FPGAs. However, to get high performance for these kernels, it is mandatory to restructure the applica-tion, to generate adequate communication mechanisms for the transfer of remote data, and to make good usage of the memory bandwidth. In the context of the high-level synthe-sis (HLS), from a C program, of hardware accelerators on FPGA, we show how to automatically generate optimized re-mote accesses for an accelerator communicating to an exter-nal DDR memory. Loop tiling is used to enable block com-munications, suitable for DDR memories. Pipelined commu-nication processes are generated to overlap communications and computations, thereby hiding some latencies, in a way similar to double buffering. Finally, data reuse among tiles is exploited to avoid remote accesses when data are already available in the local memory. Our first contribution is to show how to generate the sets of data to be read from (resp. written to) the external mem-ory just before (resp. after) each tile so as to reduce com-munications and reuse data as much as possible in the accel-erator. The main difficulty arises when some data may be (re)defined in the accelerator. Our second contribution is an optimized code generation scheme, entirely at source-level, i.e., in C, that allows us to compile all the necessary glue (the communication processes) with the same HLS tool as for the computation kernel. Both contributions use advanced poly-hedral techniques for program analysis and transformation. Experiments with Altera HLS tools demonstrate how to use our techniques to efficiently map C kernels to FPGA