Add to ORKGAbstract—Theoretical analysis of bus-invert coding for reducing switching activity was previously investigated. In this paper we conduct a theoretical analysis of this method for coupling reduction. Closed-form formulas are derived to compute the number of couplings per bus transfer for a non-partitioned versus a partitioned bus. Our contribution complements the work done previously and helps establish a sound theoretical foundation for bus-invert coding. I
Previously reported bus encoding approaches reduce crosstalk delay but they ignore the effects of in...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
The authors propose a partial bus-invert coding scheme that reduces the total number of bus transit...
In this paper we introduce new knowledge about bus invert coding schemes. We give a condition on the...
The selection of the right low-power coding technique during the design of the interconnect architec...
The coupling capacitances between on-chip bus lines become dominant in deep-submicron technologies. ...
<p>Multiplexing parallel busses into serial links has been proposed for its advantages such as reduc...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
Dynamic power dissipation on I/O buses is an important issue for high-speed communication between ch...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed wid...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
As device geometries shrink, power supply voltage decreases, and chip complexity increases, the nois...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
Previously reported bus encoding approaches reduce crosstalk delay but they ignore the effects of in...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
The authors propose a partial bus-invert coding scheme that reduces the total number of bus transit...
In this paper we introduce new knowledge about bus invert coding schemes. We give a condition on the...
The selection of the right low-power coding technique during the design of the interconnect architec...
The coupling capacitances between on-chip bus lines become dominant in deep-submicron technologies. ...
<p>Multiplexing parallel busses into serial links has been proposed for its advantages such as reduc...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
Dynamic power dissipation on I/O buses is an important issue for high-speed communication between ch...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed wid...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
As device geometries shrink, power supply voltage decreases, and chip complexity increases, the nois...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
Previously reported bus encoding approaches reduce crosstalk delay but they ignore the effects of in...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...