SoC On-Chip Bus Debug/Monitoring Infrastructure

Debugging in the System-on-a-Chip (SoC) environment is challenging since it is hard to observe their signals on a chip and not efficiently to verify on-chip bus protocols. This demonstration shows how we can enable the SoC debugging and performance evaluation with the reverse-encoding-based on-chip bus tracer [1] and on-chip bus protocol checker.[2] Traditional simulation-based bus protocol monitors can check whether the bus signals obey bus protocol or not. But they still lack of efficiency for debugging mechanisms. To solve this problem, we propose a rule-based synthesizable AMBA bus protocol checker to check the bus protocol violation in real time, and once the protocol checker find the violation that will notify the bus tracer. By embedding bus tracer to an SoC, designers can observe and debug the SoC internal states easily. The bus tracer supports both Pre-Triggering (Pre-T) trace and Post-Triggering (Post-T) trace at high compression ratio. The Post-